Schematic Capture

Overview#

Schematic capture is the first design stage. You build a logical description: which components exist, which pins are tied together, and what values they have. Quality here determines everything downstream. A tidy schematic with correct net names, values and footprints makes layout nearly mechanical; a sloppy one multiplies errors.

Where to find it#

• Open an electronics design and select the schematic document tab.
• The Schematic Design toolbar groups the tools: Place > Place Components, Connect (Net, Add Bus, and others), Label, Invoke, Modify tools such as Move, Copy, Delete, Rotate, Mirror, and the Validate toolbar (ERC, Errors, Class, Synchronize). The command line accepts the same names.
• Sheets are managed in the Sheets persistent panel, opened with Sheets at the bottom of the schematic window; right-click in it and choose New to add a blank sheet, or Remove on a selected sheet.
• Press Esc to end the active command (for example, to stop drawing nets).

Step by step#

1. Set the grid. Use the default 0.1 inch grid for schematic work so pins line up. Changing grid mid-design is a classic cause of pins that look connected but are not.
2. Place parts. On the Schematic toolbar choose Place > Place Components to open the Place Components panel (it lists components from your active libraries; the dropdown can limit it to components already used in the design). Double-click a component to open the Add dialog, adjust its orientation if needed, then click on the canvas to place it; keep clicking for copies and click Done when finished. Add libraries through Open Library Manager.
3. Name and value. Parts get automatic names (R1, C1, U1). Use Name to rename and Value to set values like 10k or 100nF. Consistent naming helps the BOM.
4. Draw nets. Choose Net on the Schematic Design toolbar, click the start point, click each bend, and click the end point; press Esc to stop. The Net dialog lets you set Net Class, Bend style, Line style, Curve radius and Miter. Only nets carry connectivity; lines drawn with the Document-tab Line tool are graphics.
5. Junctions. A junction is created automatically when you manually join one net to another; the Junction tool places them independently. Nets that merely cross are not connected without one.
6. Label nets. Use Label to name a net (such as VCC, GND, SDA). Nets with the same name are connected, even on different sheets. In the Label dialog, turn Xref on if the net goes to another sheet and you want the label to record where it connects (this needs a frame with column/row classification on both sheets).
7. Power and ground. Place power supply components (for example GND, +5V) from the Place Components panel; the supply symbol names the net.
8. Buses. Choose Connect > Add Bus, draw the bus (double-click to end), then in the Bus dialog pick a predefined bus or In Design, set the alias, and move nets from Available to Included (names can use ranges such as A[0..31]). To connect nets, right-click the bus and choose Breakout Bus. Buses are conceptual: only nets define electrical connections.
9. Add sheets. For larger projects add another sheet in the Sheets panel and use named nets to link them. A schematic can hold up to 999 sheets; the Personal-use cap is covered on the limits page.
10. Check. Run ERC (see the ERC page) before moving to the board.

Options reference#

Tips and pitfalls#

Tip: Add manufacturer part number (MPN) attributes at schematic time. Retrofitting them after layout is tedious and the BOM will need them.

Warning: Nets and pins that look connected are not necessarily connected. Autodesk recommends checking with SHOW, ERC, or an exported netlist or partlist (EXPORT NETLIST / PARTLIST).

Warning: If you place a part with the wrong footprint variant, change it with the CHANGE command (package option) or use Replace; do not edit the board only.

Tip: Use hierarchical organisation on sheets: one function per sheet (power, MCU, sensors, connectors). Name nets descriptively.

Tip: For multi-gate parts, use Invoke to add further gates. Gates with Addlevel Must appear automatically, and Request gates (typically power) are only added with Invoke.

Practice exercise#

Draw a 5 V LED indicator: a connector, a series resistor sized for roughly 10 mA, an LED and ground. Use labels +5V and GND. Add a second sheet containing a decoupling capacitor tied to the same nets by name. Run ERC and confirm no unresolved errors.

Worked example: sizing and wiring a complete small schematic#

Take a 3.3 V light sensor that reports over I2C. Parts: a 3.3 V LDO (input 5 V), two 10 uF capacitors, one 100 nF capacitor per IC supply pin, an I2C sensor, two 4.7 kohm pull-ups and a 4-pin header (3V3, GND, SDA, SCL).

1. LED-free sizing check. I2C pull-ups: with 3.3 V and a 3 mA sink limit, the minimum is (3.3 - 0.4) / 0.003 = 967 ohm; with a 100 pF bus and a 100 kHz standard-mode rise-time limit of 1000 ns, the maximum is 1000 ns / (0.8473 x 100 pF) = 11.8 kohm. 4.7 kohm sits inside both limits.
2. Place and name. Put the LDO left, the sensor right, and the header on the far right. Name the resistors R_SDA and R_SCL instead of R1/R2 if you want readable netlists; the BOM groups by value either way.
3. Power. Place +5V, +3V3 and GND symbols, one per net per area. Power symbols with the same name connect everywhere in the design, on every sheet.
4. Signals. Draw SDA and SCL as nets from the sensor pins to the header and label both ends with the same name. Label rather than draw long wires; it keeps the sheet readable and the net names carry into the board.
5. Run ERC. Expect warnings about the power pins of the LDO and sensor if their pin type is pwr and nothing drives the net; fix with a power flag or by placing the supply symbol as described on the ERC page.

Net naming rules that save time#

• Use short uppercase names with no spaces: SDA, SPI_MOSI, VBUS. Spaces and punctuation other than underscore cause trouble in scripts and in exported netlists.
• Add a suffix for active-low signals, such as RESET_N, because an overbar in a text label does not carry into the net name.
• Avoid names that differ only by case or by a stray character (SDA and Sda, GND and GND1): they look alike on screen but can be different nets. Confirm with SHOW.
• For differential pairs use USB_DP/USB_DM or CLK_P/CLK_N; later net classes and length matching rely on the names.
• Give any net you intend to measure with a test pad a specific name, so it is easy to find with SHOW.

Multi-sheet strategies#

A net crossing sheets does not need an off-page connector; the same name alone connects it (Autodesk: nets with the same name are connected even on different sheets). SHOW on the net lists which sheets it appears on. Personal use is commonly reported as limited to two sheets (see the limits page), so reserve sheet 2 for blocks with the fewest external connections.

Multi-gate parts, power pins and invisible supply#

Logic ICs and op-amps are often split into gates plus a separate power gate. Place all required gates; ERC will flag missing ones through unconnected pins. Some libraries hide supply pins on the symbol and tie them to a net by name (typically VCC/GND); Autodesk documents an Override power supply default value option for components. If the supply name does not match your net name the part can connect to the wrong rail or to nothing. Check the part's properties and pin list, and fix it in a copy of the component in your own library (see the libraries page).

Sizing and naming components from a real calculation#

Series resistor for an indicator LED: R = (Vsupply - Vf) / I. With 5 V, Vf = 2.0 V and a target of 10 mA, R = 300 ohm; choose the nearest E24 value, 330 ohm, giving 9.1 mA. For a 3.3 V supply with a blue LED (Vf near 3.0 V), R = (3.3 - 3.0) / 0.005 = 60 ohm for 5 mA, but the margin is small; at the worst-case Vf spread of 2.8 to 3.2 V the current ranges from 8.3 mA to 1.7 mA, so the brightness varies a lot. Recording such assumptions in the part's attributes (for example NOTE: 5 mA at 3.3 V) makes later reviews faster.

Decoupling: one 100 nF X7R capacitor per supply pin placed within 3 mm of the pin, plus 10 uF bulk per regulator output. Put them on the schematic next to the part they serve so you remember to place them next to it on the board.

Failure modes and fixes#

Practice exercise#

Capture the light-sensor schematic above on one sheet, then answer these checks with the tool rather than by eye.

1. Place the 9 physical parts (LDO, sensor, 2 x 10 uF, 2 x 100 nF, 2 x 4.7 kohm, header) and confirm the count with the BOM export.
2. Use SHOW SDA and confirm the sensor pin, one pull-up and the header pin highlight.
3. Introduce a deliberate error by changing one SDA label to SDA1. Run ERC and use SHOW SDA to see which pins dropped off the net. Fix it.
4. Move the header to a second sheet and confirm the board is unchanged.
5. Add MPN and SUPPLIER attributes to the sensor and export the BOM; confirm the columns are present.

Related#

• Electronics Overview
• Libraries, Symbols, Footprints and Devices
• ERC, Design Rules and DRC