ERC, Design Rules and DRC

Overview#

Two automated checks protect you from expensive mistakes.

• ERC (Electrical Rule Check) inspects the schematic: unconnected pins, conflicting pin directions, missing power, duplicate part names, nets with a single pin.
• DRC (Design Rule Check) inspects the board against design rules: copper clearance, copper width, drill size, annular ring, solder mask and stencil openings, silkscreen-to-mask clearance, board outline clearance, acute angles, wire stubs and unrouted airwires. DRC runs live as you edit (Live DRC) and manually on demand.

Passing ERC and DRC does not prove the circuit works, only that it obeys the rules you configured. The rules must match what your fabricator can build.

Where to find it#

• ERC: on the Schematic Validate toolbar click ERC (or type ERC). Results appear in the ERC Errors panel; Errors reopens the results of the last run.
• Design rules: on the 2D PCB Rules toolbar click Rules > Design Rules. DRC: Rules > Check Design Rules (or type DRC); results appear in the Errors panel (type ERRORS to open it).
• Design preferences (Preferences > Design Preferences) hold the Layer Stack, Shapes, Supply, Drill Legend and Designators settings; they describe the manufacturing basis of the design and are not checked as rules.
• Manufacturers can supply a design rules file (.DRU); Autodesk says to load it before layout, especially before routing. Fusion saves its own rules as a Fusion Electronic Design Rule (.edru) file. Autodesk's pages do not name the exact load button, so look in the Design Rules dialog.

Step by step#

ERC#

1. Open the schematic and run ERC.
2. Read the list. Errors are serious; warnings need judgment. Selecting an entry highlights its location.
3. Fix real problems (unconnected pins, wrong pin direction, missing supply), then click Refresh. Where a warning is intentional (a deliberately open pin), select it and click Approve; Approve all works on the Errors or Warnings heading and Disapprove all on the Approved heading. Pins can also be marked as intentionally unconnected.
4. Re-run until only approved items remain.

Design rules and DRC#

1. Switch to the 2D PCB and choose Rules > Design Rules, then General Rules.
2. Select a rule category, enter its Minimum (and Preferred, which must not be smaller) value and tick Enabled. Or load the fabricator's rules file before you start routing.
3. Check the stack-up in Design > Layers > Layer Stack Manager (or Preferences > Design Preferences > Layer Stack).
4. Click Rules > Check Design Rules (or run DRC) and review the Errors panel.
5. Select an error to locate it. Fix the cause, not just the symptom. Re-run until clear.
6. Run DRC again after any change, and always immediately before generating manufacturing files.

Options reference#

Design Preferences tabs (not checked as rules): Layer Stack, Shapes, Supply (thermal isolation and thermal symbols for vias), Drill Legend, Designators. Under Misc in General Rules, Check angle (0/45/90/135 degree tracks) is off by default and Check restrict is on by default. Net classes are reviewed with the Class button on the Schematic Validate toolbar (Classes tab to add classes and move nets, Rules tab for width and clearance); Custom Rules can scope a rule with In Net Classes, In Signal, In Diff Pair, In Component, On Layers and similar scopes, with priority order deciding which rule matches first.

Tips and pitfalls#

Warning: Default design rules are a starting point, not your fabricator's. Always load or enter the real minimums before routing, otherwise you route first and fix everything later.

Tip: Set a net class for power with wider traces and larger clearances, and assign it before routing; Autodesk's autorouter honours net classes. Custom rules with the In Net Classes scope apply to manual routing too.

Warning: Approving errors hides them. Only approve an error when you can say exactly why it is acceptable.

Tip: Run Re-fill Copper Pours before DRC and before exporting CAM files, so the checks see current pour shapes (Autodesk recommends this when auto-pour is off).

Tip: ERC and DRC are independent. An unconnected pin that ERC flagged will appear on the board as a missing airwire or silently be absent; fix in the schematic first.

Practice exercise#

Take the LED circuit from the schematic page. Introduce a deliberate error: delete the ground net from the LED. Run ERC and note the report. Fix it. On the board set the Copper Clearance minimum to 0.2 mm, route a trace with a 0.1 mm gap to a pad, and confirm that DRC reports it.

Reading ERC output#

ERC messages fall into a few families. The table below is general guidance on typical findings, not a list of Fusion's exact message texts (Autodesk's help does not enumerate them).

Pin direction (set in the library: nc, in, out, io, oc, pwr, pas, hiz, sup) is what ERC works from. If a library marks every pin as passive (pas), ERC loses most of its power; for custom parts, set directions properly.

Worked example: a clearance budget for a hobby fab#

Assume your fabricator quotes a 0.15 mm minimum trace width, 0.15 mm minimum clearance, 0.3 mm minimum drill and 0.15 mm minimum annular ring. A conservative hobby set adds margin of about 30 percent: width 0.2 mm, clearance 0.2 mm, drill 0.4 mm, annular ring 0.15 mm.

• A via with 0.4 mm drill and 0.15 mm ring has a diameter of 0.4 + 2 x 0.15 = 0.7 mm. Check that a via fits between two 0.5 mm-pitch pads: 0.5 mm pitch with 0.25 mm pads leaves 0.25 mm gap, so a 0.7 mm via cannot sit between them.
• A TSSOP-20 with 0.65 mm pitch and 0.35 mm pads leaves 0.30 mm between pads. One 0.2 mm trace needs 0.2 mm + 2 x 0.2 mm clearance = 0.6 mm, so you cannot pass a trace between adjacent pads. You must fan out to the outside.
• A 0.2 mm trace and 0.2 mm clearance give a 0.4 mm routing pitch, which is 25 tracks per 10 mm channel at best, and 12 to 15 in practice.

Entering these numbers before routing turns DRC from a late surprise into a live constraint (Live DRC runs at the end of interactive workflows). The numbers are an example, not Autodesk data.

Net classes in practice#

Create classes with the Class dialog (Schematic Validate toolbar > Class), then assign nets to them. The values below are example general guidance, not Autodesk defaults:

Current capacity estimate (general guidance, not Autodesk data; 1 oz copper, 10 degree C rise, external layer): about 0.3 A at 0.2 mm, 0.6 A at 0.5 mm, 1.0 A at 1.0 mm. Compare with an IPC-2221 calculator for your actual copper weight and allowed rise.

A net class applies to the net, not to the wire; keep the class associations in mind when you rename nets.

The DRC check list in detail#

After DRC runs, results appear in the Errors panel (Errors and Warnings tabs). A short triage method:

1. Fix copper clearance errors first; they usually mean a trace crosses or sits too close to another net.
2. Look at causes such as a copper pour isolate lower than the rule, or a trace added with the wrong net class.
3. Fix Copper Width, Drill Size and Annular Ring errors by changing parameters, not by approving. For annular ring, remember Auto Resize on produces a warning and enlarges the object, while Auto Resize off produces an error.
4. Fix Wire Stub, Air Wire and Unconnected Lines items: delete stub traces and route the remaining airwires.
5. Inspect Solder Mask - Silkscreen Clearance and mask warnings; some are tolerable, but silkscreen over an SMD pad can disturb soldering.
6. Re-run DRC and repeat until the list is empty or contains only items you can justify in writing.

For each approved error, add a note in the board description (what, why, who) so future you or a reviewer can find it.

Failure modes and fixes#

Practice exercise#

Configure a rule set, break it, and clear it.

1. In General Rules enter Copper Width 0.2 mm, Copper Clearance 0.2 mm, Drill Size 0.4 mm and an Annular Ring of 0.15 mm, and create a power net class at 0.5 mm.
2. Place a TSSOP-20 part on the board and try to route a 0.2 mm trace between pads of 0.65 mm pitch. Observe the DRC error and note the clearance reported.
3. Add a via and compute its diameter (0.7 mm); check that it fits where you put it.
4. Set the copper pour isolate to 0.1 mm on purpose and run DRC; record how many errors appear. Fix by raising isolate to 0.25 mm and refill with Re-fill Copper Pours.
5. Approve one error with a reason, then use Disapprove all and verify it returns.

Related#

• Schematic Capture
• Board Layout
• Manufacturing Outputs